1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same and, more particularly, to a semiconductor device having a multilayer structure employing a TSV, and a method for producing the same.
2. Description of the Related Art
FIG. 25 is a cross-sectional view of steps in a method for producing a conventional semiconductor device, and the steps include the following steps 1 to 5.
Step 1: as shown in FIG. 25(a), a substrate 1 is prepared and a BOX layer (buried oxide layer) 2 is deposited thereon. Then, semiconductor elements 13 of a logic circuit such as an FPGA (Field Programmable Gate Array) are formed on the BOX layer 2. The semiconductor elements include elements such as an SOI transistor having an SOI structure, and a capacitor.
Then, an insulation layer 4 is formed and an opening part is provided in the insulation layer 4 to form a via hole 5. In addition, an opening part is provided in the insulation layer 4 and the BOX layer 2 to form a TSV (Through Silicon Via) 6.
Then, a wiring layer 8 is formed and the insulation layer 4 is deposited. Then, the via hole 5 and the wiring layer 8 are formed by a process such as a damascene process. Through the above steps, a first layer 10 is produced.
Step 2: as shown in FIG. 25(b), a second layer 20 is formed. The second layer 20 is provided in such a manner that the BOX layer 2 is formed on the substrate 1, and components such as the semiconductor elements 13, the via hole 5, and the wiring layer 8 are provided thereon. The semiconductor elements 13 include a logic circuit such as the FPGA.
Step 3: as shown in FIG. 25(c), the substrate 1 of the second layer 20 is removed by a method such as a CMP method to expose the TSV 6.
Step 4: as shown in FIG. 25(d), a third layer 30 is formed. The third layer 30 is provided in such a manner that the BOX layer 2 is formed on the substrate 1, and components such as semiconductor elements 3 of an I/O circuit (input/output circuit), the via hole 5, and the wiring layer 8 are provided thereon. Then, the third layer 30 is laminated on the second layer 20 in such a manner that the wiring layer 8 of the third layer 30 comes into contact with the TSV 6 of the second layer 20.
Step 5: as shown in FIG. 25(e), the substrate 1 of the third layer 30 is removed by a method such as the CMP method. Through the above steps, a semiconductor device (three-dimensional device) 1000 having the three laminated layers M1, M2, and M3 on the substrate 1 is completed.
In the semiconductor device 1000 having the multilayer structure such as the three-dimensional device, since the TSVs 6 have a large cross-sectional area, they need to be arranged in almost a straight line in a direction perpendicular to the substrate 1, as a layout arrangement. Therefore, when the above production method is used, layouts (positions of the semiconductor elements 13 and the TSV 6) of the second layer 20 and the third layer 30 need to be almost mirror-symmetrical to a layout of the first layer 10 with respect to a plane parallel to the substrate 1.
However, in order to form the second layer 20 and the third layer 30 having the mirror-symmetrical layouts, based on the layout of the first layer 10, it is necessary to change a mask, a CAD layout, and a circuit verification tool. Especially, in the conventional method, since the second layer 20 includes the semiconductor elements 13 of the logic circuit, operations to redesign the logic circuit to be mirror-symmetrical and manufacture a corresponding mask are very complicated, which causes production cost to increase.
In view of the above circumstances, focusing on the fact that an I/O circuit (input/output circuit) is very easy to design and manufacture a mirror-symmetrical layout as compared with the logic circuit, the inventors completed the present invention in which only the I/O circuit (input/output circuit) is made in the mirror-symmetrical layout.